/*
 * Copyright : (C) 2024 Termony Technology, Inc. All Rights Reserved.
 */

#ifndef RK_VCCIO6_IOC_HW_H
#define RK_VCCIO6_IOC_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

/** @name Register Map
 *
 * Register offsets for the VCCIO6_IOC.
 */
#define RK_VCCIO6_IOC_GPIO4A_DS_L_OFFSET    0x0080U /* GPIO4A Driver Strength Control Low bits */
#define RK_VCCIO6_IOC_GPIO4A_DS_L_OFFSET    0x0084U /* GPIO4A Driver Strength Control high bits */
#define RK_VCCIO6_IOC_GPIO4B_DS_L_OFFSET    0x0088U /* GPIO4B Driver Strength Control Low bits */
#define RK_VCCIO6_IOC_GPIO4B_DS_L_OFFSET    0x008CU /* GPIO4B Driver Strength Control high bits */
#define RK_VCCIO6_IOC_GPIO4C_DS_L_OFFSET    0x0090U /* GPIO4C Driver Strength Control Low bits */
#define RK_VCCIO6_IOC_GPIO4A_P_OFFSET       0x0140U /* GPIO4A Pull-up/down Control */
#define RK_VCCIO6_IOC_GPIO4B_P_OFFSET       0x0144U /* GPIO4B Pull-up/down Control */
#define RK_VCCIO6_IOC_GPIO4C_P_OFFSET       0x0148U /* GPIO4C Pull-up/down Control */
#define RK_VCCIO6_IOC_GPIO4A_IE_OFFSET      0x01B0U /* GPIO4A Input Enable Control */
#define RK_VCCIO6_IOC_GPIO4B_IE_OFFSET      0x01B4U /* GPIO4B Input Enable Control */
#define RK_VCCIO6_IOC_GPIO4C_IE_OFFSET      0x01B8U /* GPIO4C Input Enable Control */
#define RK_VCCIO6_IOC_GPIO4A_SMT_OFFSET     0x0240U /* GPIO4A Schmitt Trigger Control */
#define RK_VCCIO6_IOC_GPIO4B_SMT_OFFSET     0x0244U /* GPIO4B Schmitt Trigger Control */
#define RK_VCCIO6_IOC_GPIO4C_SMT_OFFSET     0x0248U /* GPIO4C Schmitt Trigger Control */
#define RK_VCCIO6_IOC_GPIO_PDIS_OFFSET      0x028CU /* Auto Pull-up/down disable Control */

#ifdef __cplusplus
}
#endif

#endif /* RK_VCCIO6_IOC_HW_H */